Google's Coral NPU Architecture Reaches Completion With Open Compiler and Commercial Silicon Partners

Artificial intelligence is increasingly running on devices rather than in distant data centers. Wearables, robots, and smart sensors need to make decisions instantly with minimal power consumption and complete privacy—requirements that cloud-dependent systems cannot meet. Google Research has now reached critical milestones on an effort to standardize how AI software and hardware work together at the edge.

The Fragmentation Problem at the Edge#

Building machine-learning systems for edge devices has traditionally been fragmented and inefficient. While cloud computing has converged around a handful of proven software stacks, edge hardware spans hundreds of incompatible chip designs and proprietary toolchains. Developers face a significant burden: they must rewrite computational kernels, re-optimize models, and debug compiler quirks for each new processor they want to support. This "fragmentation tax" slows product cycles and discourages broader adoption of edge AI.

Coral NPU: An Open Standard Approach#

Google introduced Coral NPU last year as a response to this problem—an open-standard hardware and software architecture designed to unify the fragmented edge market. Built on a RISC-V foundation, the platform combines a standards-based instruction set with an open-source compiler. The goal is straightforward: developers can optimize their model once and deploy it across different silicon vendors and device types without major rewrites.

Four Hardware Milestones Now Complete#

Google announced today that the full 32-bit Coral NPU architecture is complete, incorporating four major design phases:

• Milestone 1–3 (released previously): A C-programmable RISC-V scalar core for control logic, an RVV v1.0 vector co-processor for single-instruction-multiple-data operations, and a tightly coupled memory subsystem with floating-point support
• Milestone 4 (released today): A dedicated Matrix Execution Unit configured for up to 1 TOPS (trillion operations per second) while targeting 10 milliwatts of average power

The Matrix Execution Unit is the key innovation. Modern ML workloads—particularly vision and transformer models—spend most cycles multiplying matrices. A traditional vector processor must repeatedly load weights from memory, consuming far more energy on data movement than on computation. The new unit uses a dedicated outer-product multiply-accumulate engine that computes a full 2D tile per cycle (256 operations at a time), reusing weights and activations directly in local registers. This design change allows wearables to run richer workloads—voice translation, spatial audio processing, and real-time visual perception—on a single battery charge.