New Approach Brings Real-Time Tracing to VDM-SL Software Specifications

Formal specification languages like VDM-SL have long supported rigorous verification of software through mathematical proof and simulated testing. A new research direction aims to add persistent, analyzable visibility into how operations actually execute by recording their internal behavior as traces.

Current VDM Verification Practices#

VDM already offers several ways to validate specifications. Interpreters enable animation of specifications to confirm they behave as intended. Debuggers let developers step through operations one action at a time to observe internal state changes. However, these insights remain ephemeral—once the session ends, the operational details are lost.

Recording Execution Traces for Persistent Analysis#

The proposed approach captures three key execution events: variable assignments, operation calls, and return statements. By recording these traces systematically, developers gain a persistent record of how an operation's internal state evolved during execution. This data can then be organized as a state-based model for deeper analysis and understanding.

Implementation and Visualization#

The researchers have implemented the execution trace framework in ViennaTalk, a tool for working with VDM specifications. Their work also explores how these recorded traces can be visualized—turning raw execution logs into human-readable models that help developers comprehend complex operational behavior at a glance.

This bridges a gap between VDM's existing static verification methods and runtime observability, enabling more thorough validation of formal specifications.