Agentic AI Framework Automates Hardware Verification with Iterative Feedback Loops

Hardware design verification—particularly the creation of register-transfer level (RTL) testbenches—represents a significant bottleneck in modern chip development. While language models have shown promise in automating this task, traditional single-shot prompting often yields testbenches that either fail to run, don't match the design's actual behavior, or leave critical code paths untested.

A new research effort proposes AgentDV, an agentic framework that treats verification as an iterative problem rather than a one-time generation task. Instead of asking an LLM to produce a complete testbench in a single attempt, the system chains together analysis, construction, simulation, measurement, and refinement cycles—with each step grounded in real hardware feedback.

How It Works#

The framework introduces three core mechanisms to improve testbench quality:

• Runnability filtering catches syntactically or logically invalid generated code before it wastes simulation time
• CSR-grounded checking (using control and status registers) reduces the hallucinated signals and incorrect expected behaviors that plague naive generation
• Coverage-guided iteration uses measured test coverage gaps to prompt the model to regenerate and extend test cases

This closed-loop design allows the AI to learn from simulation failures and coverage shortfalls, progressively refining the verification environment toward completeness.

Evaluation Results#

Testing on industry-relevant designs including OpenTitan security blocks showed striking differences between single-shot and iterative approaches. Direct LLM prompting failed to produce any valid, coverage-producing environment on the benchmarks tested.

AgentDV achieved varying results depending on the underlying model:

• Claude Sonnet 4.6: 80.9% average pass rate across all test designs, with 100% success on four designs; 74.5% line coverage and 88.4% branch coverage on average
• Llama: 58.7% pass rate; 69.1% line coverage and 82.3% branch coverage
• Qwen: 60.6% pass rate; 64.9% line coverage and 76.7% branch coverage

The higher performance with more capable models suggests that the framework's effectiveness depends on the LLM's ability to interpret feedback and adapt its generation strategy accordingly.

Implications#