AI system automates translation of vectorized code from ARM to RISC-V architecture

A new approach to cross-architecture code translation uses large language models to automatically convert vectorized intrinsic functions between different processor instruction sets. The technique, called IntrinTrans, addresses a longstanding challenge in software optimization where libraries must be rewritten for new hardware platforms.

The Problem#

Mainstream software libraries often rely on hardware-specific intrinsic functions—low-level code optimized for particular processor features—to achieve high performance. When a new processor architecture emerges, developers typically face a choice between rewriting this code manually or using simplistic rule-based translation systems. Both approaches are labor-intensive and error-prone, slowing adoption of new platforms like RISC-V.

How IntrinTrans Works#

The system takes a novel approach by pairing an LLM with a compile-and-test feedback loop. Rather than attempting perfect translation in a single pass, the model generates code, the system tests it against a compiler and execution environment, and the LLM refines its output based on the results. The tool further optimizes the final intrinsic functions by analyzing register usage patterns through liveness analysis—a compiler technique that tracks which variables remain in use at each point in the program.

Tested Results#

Researchers evaluated IntrinTrans by translating a vectorized benchmark originally written for ARM Neon intrinsics into RISC-V Vector (RVV) intrinsics. Performance depended on which underlying LLM powered the translation, with success rates ranging from 47% to 100%. The generated code matched the speed of hand-written native implementations, delivering between 0.85x and 1.28x performance relative to optimized baselines—a result competitive enough for practical deployment.

Significance#

The work demonstrates that advanced language models can reliably handle the semantic and syntactic constraints of hardware-specific code when given iterative feedback. This approach could accelerate adoption of emerging processor architectures by automating time-consuming translation tasks that currently require expert engineers.