IBM unveils sub-1 nanometer chip architecture for AI data centers

IBM has announced a new chip architecture that packs nearly 100 billion transistors onto a fingernail-sized die—roughly twice the density of its prior generation—while dramatically improving energy efficiency. The company calls it the world's first sub-1 nanometer chip technology for AI workloads.

IBM's Jay Gambetta, director of IBM Research, framed the leap as transformative: computing power would grow substantially without matching increases in energy consumption.

What "sub-1 nanometer" really means#

The nanometer naming is more marketing finesse than literal physics. It's physically impractical to build reliable transistors smaller than 1 nanometer. Instead, IBM's new "nanostack" architecture simulates the performance gains one would expect from a hypothetical sub-1 nanometer chip. IBM calls this the 0.7-nanometer or 7 angstrom node (since 1 nanometer = 10 angstroms).

These node designations no longer correspond to actual physical feature sizes—that stopped being true decades ago. Older chips from the 1970s–80s had features matching their process name (like 180-nanometer chips with 180-nanometer features), but modern 3-nanometer or 2-nanometer processes bear no such relationship to reality.